Method and device to process digital media streams

ABSTRACT

A digital processing device to process media data is provided. The device includes a plurality of processing modules to process the media data, and a media data path. The media data path communicates the media data between the processing modules, wherein the media data path is arranged in a ring configuration. In one embodiment, the media data path defines a digital audio bus that serially interconnects the plurality of processing modules. The digital audio bus may communicate digital audio data in a plurality of time-slots, each particular processing module having an associated time-slot from which data is received from the data path for processing by the particular processing module.

FIELD OF THE INVENTION

The present invention relates generally to the field of processingdigital media data. More specifically, the invention relates to a methodto communicate media data between a plurality of processing modules andto a digital processing device to process media data.

BACKGROUND OF THE INVENTION

Conventional audio processing devices use a fixed and predetermined(hardwired) configuration to interconnect various processing componentssuch as filter components, delay components, sample rate converters(SRC), and a Digital Signal Processor (DSP). However, such aconfiguration may result in the inability to perform certain algorithmsthat require connecting the processing components in a different fashionthan the hardwired configuration allows. It may also createcommunication “bottlenecks” as the various processing components canonly communicate with each other via the DSP, if they can communicate atall. The DSP thus functions as a hub through which all data iscommunicated even if the DSP is not required to process the data.Additionally, a hardwired configuration often results in wastedprocessing power, since a signal always passes through a particularprocessing component even if the algorithm does not require thatcomponent. And if an algorithm requires more processing elements thanthe hardwired configuration provides, the algorithm cannot be performed.It will thus be appreciated that such a configuration may inhibit deviceperformance.

SUMMARY OF THE INVENTION

In accordance with the invention, there is provided a digital processingdevice and method to process media data, the device including:

-   -   a plurality of processing modules to process the media data; and    -   a data path to communicate data between the processing modules,        wherein the data path is arranged in a ring configuration.

The invention extends to a machine-readable medium embodying a sequenceof instructions that, when executed by a machine, cause the machine tocarry out any of the methods described herein.

Other features of the present invention will be apparent from theaccompanying drawings and from the detailed description that follows.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is now described, by way of example, with reference to theaccompanying diagrammatic drawings. In the drawings,

FIG. 1 shows a schematic block diagram of an exemplary digitalprocessing device, in accordance with one embodiment of the invention,including a data path arranged in a ring configuration;

FIG. 2 shows a schematic block diagram of a further embodiment of adigital processing device, also in accordance with the invention;

FIG. 3 shows a schematic block diagram of a routing controller, inaccordance with an embodiment of the invention, for routing digital datain the digital processing device of FIG. 2;

FIG. 4 shows a schematic block diagram of an exemplary interface betweena routing controller and a digital signal processor (DSP) of the digitalprocessing device;

FIG. 5 shows a schematic block diagram of a processing module interface,according to an embodiment of the invention;

FIG. 6 shows an exemplary time-slot location arrangement of the datapath of FIG. 2;

FIG. 7 shows an exemplary linked list of an input mapper; and

FIG. 8 shows a schematic flow diagram of a method, in accordance withthe invention, for communicating data in a digital processing device.

DETAILED DESCRIPTION

A method and device to process digital media data, is described. In thefollowing description, for purposes of explanation, numerous specificdetails are set forth in order to provide a thorough understanding ofthe present invention. It will be evident, however, to one skilled inthe art that the present invention may be practiced without thesespecific details.

Referring to the drawings, reference numeral 10 generally indicates aschematic block diagram of an exemplary digital processing device inaccordance with the invention. The device 10 is shown to include aplurality of processing modules, namely, a digital signal processing(DSP) module 12, a delay module 14, a sample rate converter (SRC) module16, a filter module 18, and a mixer module 20. The modules 12 to 20 areinterconnected serially via a data path 22 which is arranged in a ringconfiguration wherein data is sequentially communicated from any oneprocessing module to any other processing module. Unlike conventionaldigital processing devices, the device 10 in accordance to the inventionallows each module 12 to 20 to communicate data with any other module 12to 20 connected to the data path 22 as described in more detail below.In one embodiment of the invention, the data path 22 is time divisionmultiplexed wherein a routing controller controls communication of databetween the various modules 12 to 20. Further, it is to be appreciated,that the modules 12 to 20 are merely exemplary modules and furthermodules (with the same or differing processing capabilities) may beincluded in the device 10 and/or any one or more of the modules 20 maybe removed and, for example, included within any other module 12 to 20.

Thus, in one embodiment, any one of the modules 12 to 20 may communicatedata to any one or more of the other modules 12 to 20 under control of arouting controller. Accordingly, data being processed by the digitalprocessing device 10 may be flexibly routed between different modules 12to 20 and need be not restricted to predetermined pathways as in thecase of conventional devices. It will be appreciated that a module 12 to20 and 34 may also communicate data back to itself via the audio bus 46.Accordingly, repeated processing may be performed on the data by thesame processing module. The processing module 12 to 20 that provides thedata to the data path 22 may be viewed as a source processing module,and the particular processing module 12 to 22 that is to process thedata may be viewed as a target or destination processing module. As aprocessing module 12 to 20 may return processed data to itself, in onemode of operation a processing module 12 to 20 may define both thesource and destination processing module. Thus, for example, the filtermodule 18 may form a cascaded filter arrangement where its output orprocessed data may be sent back to itself for further processing priorto being sent to another processing module 12 to 20 and 34.

Although, the invention is described with reference to processing adigital media stream in the form of a digital audio stream, it ishowever to be appreciated that the invention may be applied to theprocessing of any other digital media streams, for example, digitalvideo streams or the like.

Referring in particular to FIG. 2 of the drawings, reference numeral 30generally indicates a digital processing device in accordance with afurther embodiment of the invention. The device 30 resembles the device10 and, accordingly, like reference numerals have been used to indicatethe same or similar feature unless otherwise indicated.

The device 30 includes a DSP module 12, a delay module 14, a sample rateconverter (SRC) module 16, a filter module 18, and a mixer module 20that are substantially similar to the modules described herein before.Further, the device 30 includes an audio memory transport module 32 anda digital audio input output (I/O) module 34. The audio memory transportmodule 32 communicates via a bus 36 with an interface module 38 which,for example, may form part of a bus of a computer device (for example apersonal computer or PC). In one embodiment, the interface module 38includes a bridge 40 and two PCI-X bus interfaces 42 that interface thebridge 40 to a conventional PC bus 44. The digital I/O module 34 mayreceive a digital audio input and provide digital audio output to anoutput device. As in the case of the device 10, the device 30 includes adata path 22 which serially interconnects the modules 12, 34, 32 and 14to 20.

The data path 22 of the device 30 includes a media data path in theexemplary form of an audio data path or audio bus 46, and a processingcontrol path in the exemplary form of a parameter bus 48. In oneembodiment, both the audio bus 46 and the parameter bus 48 are arrangedin a ring configuration wherein data is communicated between the variousprocessing modules 12 to 20, 32, 34 in a time division multiplexedfashion. As the various modules are located along the audio bus 46,audio data may be routed between modules without requiring the data tobe routed through a central hub (e.g., a DSP). In certain embodiments,the device 30 includes a transport bus 50 which interfaces an externalcomputer via the interface module 38 and the audio memory transportmodule 32 to the processing modules 12 to 20.

In order to control the routing of data on the data path 22 (including,for example, the audio bus 46, the parameter bus 48 and the transportbus 50) the device 30, in certain embodiments, includes a routingcontroller 52 (see FIG. 3) which controls the routing of data along thedata path 22. In particular, as generally indicated by reference numeral54, in one embodiment the routing controller 52 controls the routing ofdata to each processing module 12 to 20, 32, 34 via chip select lines 56and address, write data, and write enable lines 58. Each module 12 to20, 32, 34 communicates data to the routing controller 52 via read dataand acknowledge lines 60. In one embodiment, the routing controller 52defines a host interface that uses a full synchronous hand-shakeapproach that interfaces the various processing modules 12 to 20, 32, 34of the device 30. For example, the routing controller 52 may generate achip select that is held active until an acknowledge signal is receivedfrom a selected processing module 12 to 20, 32, 34. In one embodiment,the routing controller 52 decodes the most significant bits of a hostaddress and, in response thereto, generates a chip select that enablesthe selected processing module 12 to 20, 32, 34. As described in moredetail below, each module 12 to 20, 32, 34 may locally decode theremaining least significant bits of the hosts address that aresignificant thereby to identify the specific module 12 to 20, 32, 34 towhich data is to be routed.

The exemplary routing controller 52 of FIG. 3 uses a common data bus 58to provide address, write data and write enable data to all of theprocessing modules 12 to 20, 32, 34. However, each module 12 to 20, 32,34 includes a dedicated read data and acknowledge bus 60 for readingdata and providing acknowledgements to the routing controller 52.

In one embodiment of the invention, the DSP module 12 is interfaced tothe routing controller 52 in such a fashion so that the DSP module 12has access to registers and random access memory (RAM) provided in eachof the modules 14 to 20, 32, 34. In particular, as shown in FIG. 4, theDSP module 12 may communicate with the routing controller 52 via a databus 62, an address bus 64, acknowledge lines 66, write enable lines 68,a request line 70 and a chip select line 72. In order to accessregisters and RAM that may be provided in the modules 14 to 20, 32, 34,the DSP module 12 communicates a request via line 70 to the routingcontroller 52. The routing controller 52 may then acknowledge therequest via the acknowledge line 66 where after the requestedfunctionality may be executed using the address bus 64 and data bus 62.

In embodiments in which a sample rate tracker is provided within thedigital audio I/O module 34, it may also be interfaced to the routingcontroller 52 thereby providing access to registers and/or RAM in themodules 12 to 20, 32. In one embodiment, the routing controller 52treats requests from the DSP module 12 (and one or more sample ratetrackers if provided) as equivalent to host processor accesses using afirst come first served priority scheme. However, if the requests arriveat the same time, the requests may be sorted. For example, the routingcontroller 52 may first route requests to the DSP module 12, then to thesample rate trackers provided in the digital audio I/O module 34 and,finally, to a host processor. In one embodiment, the device 30 has twobase address registers, one mapped to I/O and the other mapped tomemory. Both of these registers may be active simultaneously and, bothaddress registers may allow access to the same internal registers andmemories of a chip on which the device 30 is provided.

In one embodiment of the invention, the audio bus 46 provides audiochannels that are time division multiplexed. Each processing module 12to 20, 32, 34 may have a fixed output time-slot allocated to it and aprogrammable or variable input time-slot. Thus, in this embodiment, themodules 12 to 20, 32, 34 may always output data in the samepredetermined time-slot to the audio bus 46 but receive data indifferent time-slots under control of the routing controller 52. Thus,as the input time-slot associated with each individual module 12 to 20,32, 34 is programmable, data may be routed between the various modules12 to 20, 32, 34 in a flexible fashion. As described in more detailbelow, a channel identification bus may be provided to identify themodule 12 to 20, 32, 34 with which the time-slot is associated. In oneembodiment, the channel identification bus identifies a sourceprocessing module 12 to 20, 32,34 and a target or destination processingmodule 12 to 20, 32, 34 includes a list to identify data sources fromwhich data is to be processed. However, it will be appreciated that thechannel identification may also identify a target processing module 12to 20, 32, 34.

In certain embodiments, the device 30 allows digital data (e.g., digitalaudio data) to be communicated along the audio bus 46 at differingsample rates (e.g., sample rates set by the DSP module 12). For example,in one embodiment of the invention, 4096 buffer channels or time-slotsare provided on the audio bus 46. In this exemplary configuration, theaudio bus 46 may then support sample rates of up to 384 kHz byallocating one time-slot for 48 kHz, two time-slots for 96 kHz, fourtime-slots for 192 kHz, and eight time-slots for 384 kHz. Thus, sincethere are 4096 total channels or time-slots in the given sample, only2048 channels or time-slots are available at 96 kHz, 1024 time-slotsavailable at 192 kHz, and 512 time-slots are available at 384 kHz. Itis, however, to be appreciated that the number of time-slots for eachsample rate at any given time during operation of the device 30 may varyand, for example, situations could arise where, for example, 3348 48 kHztime-slots are provided, 204 96 kHz time-slots are provided, and 85 192kHz time-slots may be provided. However, the various configurations(e.g., bit-rates) or numbers of time-slots may vary depending upon thefunctionality to be executed by the device 30. For example, in otherembodiments programmable operating clock frequencies may be provided.For example, clock frequencies of 150 MHz, 175 MHz, and 200 MHz may beprovided that correspond to 3072, 3584, and 4096 time-slotsrespectively. It is, however, to be appreciated that these are merelyexamples of frequencies and time-slots and that they may change fromembodiment to embodiment. Thus, in one embodiment, the media data pathmay include a total number of time-slots for communicating media data ata plurality of different bit rates wherein the sum of a number oftime-slots allocated to each one of the plurality of bit rates equalsthe total number of time-slots.

In certain embodiments, arbitrary sample rates, such as the CD standardof 44.1 kHz, may be communicated or routed via the audio bus 46 using aindicator bit (e.g. a valid bit) that indicates to a receiving module 12to 20, 32, 34 that a new valid sample is to be retrieved or extractedfrom the audio bus 46 for processing. When an arbitrary sample rate(such as the 44.1 kHz sample rate) is communicated via the audio bus 46,and the exemplary valid bit is high, the respective module 12 to 20, 32,34 may accept the data as valid. Whereas, when the valid bit goes low,the module 12 to 20, 32, 34 is thereby informed that the subsequentsamples may be disregarded.

Although in one embodiment variable sample rates may be communicated viathe audio bus 46, the parameter bus 48 may communicate control data at afixed sample rate (e.g. 48 kHz) that may be independent of the samplerate of the audio bus 46.

In one embodiment, the audio bus 46 communicates audio data to beprocessed by the various modules 12 to 20, 32, 34. However, theparameter bus 48 includes parameter or processing data which is used byan associated module 12 to 20, 32, 34 to define the functionality (e.g.,algorithm) of the associated module 12 to 20, 32, 34. Accordingly, thecontrol data may thus control how the data on the audio bus 46 will beprocessed by the particular module 12 to 20, 32, 34. For example, theparameter bus 48 may be used to communicate filter parameters to thefilter module 18, sample rate conversion parameters to the sample rateconverter module 16, delay data to the module 14 that defines the periodby which the digital audio will be delayed, and so on. It will thus beappreciated that, in order to reduce any processing latencies in thedevice 30, the parameter data should be provided to each of theprocessing modules 12 to 20, 32, 34 prior to the time slot which eachparticular processing module 12 to 20, 32, 34 is to output processedaudio data. Accordingly, as described in more detail below, parameterdata is communicated via the parameter bus 48 to a particular processingmodule 12 to 20, 32, 34 prior to the audio data arriving at theprocessing module 12 to 20, 32, 34 via the audio bus 46.

In one embodiment of the invention, audio data communicated via theaudio bus 46 is in 32-bit IEEE floating-point format (single precision).Any module placed on the data path 22 that operates in a fixed-pointformat (e.g., fixed-point audio) may thus be required to perform aconversion to and from floating-point format. As the fixed-point formatis defined to be in a range of −1 to +1, any hardware conversion of thefixed-point format will saturate floating-point values that lie outsidethis range. Accordingly, the mixer module 20 may be used to scale anydigital data that is placed on the data path 22 for any processingmodule that performs fixed-point conversion so that the conversion lieswithin the range of −1 to +1. For example, in one embodiment of theinvention, the sample rate converter module 16 and the digital audio I/Omodule 34 may process data in a fixed-point format and, accordingly,scaling may then be required by the mixer module 20.

Referring in particular to FIG. 5, reference numeral 70 generallyindicates an exemplary data path interface provided in each processingmodule 12 to 20, 32, 34. It will also be appreciated that the data pathinterface 70 may be provided in any further processing modules that maybe added in a modular fashion to the device 30 to communicate via thedata path 22. When the data path 22 includes a media data path in theform of the audio bus 46, a processing control path in the form of theparameter bus 48, and a channel identification bus 49, the interface 70may include input registers 72, 74, 76 which clock all inputs on thedata path 22 into the respective processing module 12 to 20, 32, 34 forprocessing. In a similar fashion, output registers 78, 80, 82 clock databack onto the data path 22. Dedicated processing logic 84 is provided ineach processing module 12 to 20, 32, 34 to process the digital data,received via the audio bus 46, in accordance with the parametersreceived via the parameter bus 48. The functionality of the processinglogic 84 differs from module to module. For example, the processinglogic in the filter module 18 may define a plurality of filters (e.g.,IIR and FIR filters), the processing logic 84 in the sample rateconverter module 16 may define a sample rate converter, and so on.

In the embodiment depicted in the drawings, the channel identificationdata included in the channel identification bus 49, and the parameterdata provided by the parameter bus 48, is read by the processing logic84 as shown by lines 86 and passed on or returned to the channelidentification bus 49 and the parameter bus 48, respectively, two clockcycles later (as shown by lines 88). However, audio data provided by theaudio bus 46 may be either passed directly on to the audio bus 46 (asshown by lines 90, 92) or be replaced with processed audio data from theprocessing logic 84 (as shown by lines 94 and 92). Accordingly, the datapath interface 70 may include a multiplexer 96 that selects between thedata received via the audio bus 46 and the processed data received fromthe processes logic 84. Thus, when a particular processing module 12 to20, 32, 34 is not the target processing module 12 to 20, 32, 34 and itreceives data, the processing module 12 to 20, 32, 34 may merely passthe data along the communicating ring to the next processing module 12to 20, 32, 34. Accordingly, the data may be passed on sequentially untilit reaches the target processing module 12 to 20, 32, 34. It will beappreciated that the data passed along may form part of a stream ofmedia data that is being processed. Likewise, streams of processingcontrol data may be passed along the parameter bus 48.

Referring in particular to FIG. 6, an exemplary configuration of thedata path 22 is shown. As mentioned above, in one embodiment, the datapath 22 includes the audio bus 46, the parameter bus 48, and the channelidentification bus 49. The channel identification bus 49 may includechannel identifiers that identify both the channels or time-slotsprovided on the parameter bus 48 and the channels or time-slots providedon the audio bus 46. However, it is to be appreciated, that separatechannel identifiers may be provided for the audio bus 46 and theparameter bus 48. For example, embodiments may be provided wherein theaudio bus 46 and the parameter bus 48 each have their own channelidentification bus. In one embodiment of the invention, each channelidentifier is in the form of a hexadecimal number generated by a counterwhich has its count included in the channel identification bus 49.

Exemplary parameter definitions provided on the parameter bus 48 (seeFIG. 6) are as follows:

-   -   F_(x)=filter parameters 0 to 4 for the filter module 18;    -   Pitch=pitch of the sample rate converter module 16;    -   GPP=general purpose parameters to be used by the modules 12 to        20, 32, 34; and    -   Taddr=delay line address of the delay module 14.

Exemplary audio channel or time-slot definitions are as follows:

-   -   FILT=outputs from the filter module 18 (e.g., of an IIR filter);    -   DSP=outputs of the DSP module 12;    -   SRC outputs of the sample rate converter module 16;    -   SUM=summation node outputs of the mixer module 20;    -   DAI=digital audio inputs from the I/O module 34; and    -   Tank=data outputs from the delay module 14.

In one embodiment of the invention, as mentioned above, the leastsignificant two, three, or four bits of the channel identification datamay be used to identify the specific processing module 12 to 20, 32, 34associated with a particular time-slot and, accordingly thus identifythe particular time-slot (or time-slots) that the processing module 12to 20, 32, 34 owns. However, the most significant bits may be used toidentify a logical channel or time-slot within the particular processingmodule. For example, a filter module that can process 512 discretechannels of audio implements a plurality of 512 discrete filterchannels, each requiring its own set of filter parameters, and eachproviding its own discrete filtered audio output. In an embodiment ofthe invention that contains such a filter module, the most significant 9bits of the channel identification data may determine to which filterchannel the filter parameters belong, and which filter channel generatedthe audio.

In one embodiment of the invention, the channel identification dataprovided via the channel identification bus 49 is generated in the mixermodule 20. As mentioned above, the channel identification data maydefine a channel identifier that may be generated by a counter that runsfrom 0 to 4095 wherein each number identifies, or is associated with, aparticular channel or time-slot. Further, as mentioned above, in orderto ensure that parameters arrive at the appropriate processing module 12to 20, 32, 34 prior to the time-slot in which they are to outputprocessed audio data, the data on the parameter bus 48 may be offsetrelative to data provided on the audio bus 46.

In one embodiment of the invention, software may program the mixermodule 20. The software may then take into account that a module 12 to20, 32, 34 requires a certain amount of time to operate on incomingparameters (via the parameter bus 48) and to generate the processedaudio data which it then outputs on the audio bus 46. In theseembodiments, the appropriate parameters for the processing module 12 to20, 32, 34 are provided in a time-slot that precedes the time-slot inwhich the module outputs the audio data on audio bus 46. As differentprocessing modules 12 to 20, 32, 34 may require different parameters andtimes to process the parameters and audio, parameters associated withdifferent processing modules 12 to 20, 32, 34 may be offset by adiffering number of time-slots. For example, an exemplary offset of 96may be provided for the sample rate converter module 16, an exemplaryparameter offset of 40 may be provided for the filter module 18, and anexemplary parameter offset of 20 may be provided to the delay module 14.It is, however, to be appreciated that the offsets may differ fromembodiment to embodiment and also differ in a single embodimentdepending on the functionality or algorithm that the modules 12 to 20,32, 34 are to perform or execute.

In certain embodiments, it is necessary to buffer the audio datareceived via the audio bus 46. In particular, phase coherency is arequirement for multi-channel audio data to avoid phase cancellation andimage shifting. Phase coherency is simplified by buffering a full sampleperiod of audio data. A processing module may then process guaranteedphase coherent audio from its local audio buffer without respect to therelative intra-sample timing of data arrival and data processing. It maynot be necessary to buffer all channels received via audio bus 46, onlythose that are to be processed. To implement phase coherency, aping-pong buffer scheme can be used in which at least two buffers, “A”and B”, alternate in usage from write to read. During the first sampleperiod, the received audio data may be written to buffer “A” while theprocessing module reads from buffer “B”. At a certain time, the buffersmay swap functions so that during the next sample period, the receivedaudio data is written to buffer “B” while the processing module readsfrom buffer “A”. In certain embodiments, the delay module 14, the filtermodule 18, and the mixer module 20 may change or swap audio bufferssynchronized with their respective channel processing times. Forexample, data path or audio ring input buffers of the delay module 14may swap when the delay module 14 channel equals zero, e.g., when thedelay module 14 begins to generate the audio it will output to the audiobus 46 when the most significant bits of the channel identification areequal to zero. This may occur when the data path or audio ring channelor time-slot equals the maximum channel identification minus theparameter offset of the delay module 14. If the parameter offset isequal to 20, this delays the last 20 audio ring channels or time-slotsby an extra sample period relative to the other ring channels ortime-slots from the perspective of the delay module 14. Likewise, in thecase of the filter module 18, the last 40 audio ring channels ortime-slots may be delayed by an extra sample period to the filter module18. In certain embodiments, the mixer module 20 may delay the last 18audio ring channels or time-slots. However, in one embodiment, thesample rate converter module 16 may write audio ring data directly intoits channel caches and, accordingly, relative delay problems may not beexperienced.

As mentioned above, output time-slots (time-slots in which eachprocessing module 12 to 20, 32, 34 outputs data onto the audio bus 46)are dedicated time-slots. However, in certain embodiments, thetime-slots in which data is communicated to any one of the processingmodules 12 to 20, 32, 34 is programmable and, thus, the channelidentification data identifies the particular processing module 12 to20, 32, 34 that is to process the audio data on the audio bus 46. In oneembodiment, the parameter bus 48 has its input time-slots allocated.Further, in certain embodiments, the mixer module 20 may provide theparameters that are communicated to the various processing modules 12 to20, 32, 34 via the parameter bus 48. Accordingly, not only can data beflexibly routed from any one of the processing modules 12 to 20, 32, 34to any other one or more processing modules 12 to 20, 32, 34 but, in asimilar fashion, parameters may be flexibly routed to any of theprocessing modules 12 to 20, 32, 34. In one embodiment of the invention,the DSP module 12 can overwrite parameters on the parameters bus 48thereby allowing the DSP module 12 direct control of the functionalityexecuted or performed by the delay module 14, the sample rate convertermodule 16, the filter module 18, and the mixer module 20 (or any othermodules added to the data path 22).

As mentioned above, data included in the audio bus 46 and parametersincluded in the parameter bus 48 may be flexibly routed to theprocessing modules 12 to 20, 32, 34. In one embodiment of the invention,an input mapper in the form of a linked list 100 (see FIG. 7) isprovided. In this embodiment, the routing controller 52 (see FIG. 3)performs programmable input mapping to flexibly route audio data to thevarious processing modules 12 to 20, 32, 34. In use, the input mappermay traverse a linked list 100 of input channel identifiers 102 andinput RAM addresses 104 to determine which input channels are written towhich addresses within the input audio buffer. In one embodiment of theinvention, the linked list 100 is used and the list is arranged orsorted in an order of ascending channel identifiers regardless of theinput audio buffer address, as shown by arrows 106. A host softwaredriver may maintain the list 100.

The input mapper may, in use, load the first element in the linked list100 which may include the input channel identifier 102, the input audiobuffer address 104 and appoint it to the next element in the list. Theinput mapper then waits until the input channel identifier on thechannel identification bus 49 matches the input channel identificationfield 102 and then writes the input audio data received via audio bus 46to the designated input audio buffer address. The element of the linkedlist 100 designated by the next linked list address field 101 may thenbe loaded and the operation may be repeated. The linked list 100 may bemaintained in a circular fashion so its last element points to its firstelement of the linked list 100. On reset, for example, a default inputmapping list may be automatically written by hardware initializationlogic and host driver software may merely be required to maintain thelinked list 100. If multiple filters are provided by the filter module18, an additional level of mapping may be provided to support multiplefilters operating on the same input signal or data provided via theaudio bus 46.

The methodology described above is broadly summarized in FIG. 8 of thedrawings. Reference numeral 110 generally indicates a method ofcommunicating digital media data (e.g., digital audio data) in a digitalmedia processing device such as a digital audio processing device. Asshown at block 112, digital data is provided on the data path 22. Eachparticular processor module 12 to 20, 32, 34 then identifies if the datais associated with the particular processor module 12 to 20, 32, 34 (seeblock 114). The digital data provided on the data path 22 in block 112may include both digital audio data provided on the audio bus 46 and/orprocess control data (e.g. parameter data) provided on the parameter bus48.

As shown at decision block 116, if data on the data path 22 is notassociated with the particular processing module 12 to 20, 32, 34, thenthe data received by the particular module 12 to 20, 32, 34 is merelypassed along the data path 22. If, however, the data is associated withthe particular module 12 to 20, 32, 34 (e.g. the routing controller 52has identified that the data is to be routed to the particularprocessing module 12 to 20, 32, 34), the data (audio data and/orparameter data as the case may be) is extracted from the data path 22(see block 118). When the extracted data is parameter data, theprocessing module 12 to 20, 32, 34 uses this data to define thefunctionality (e.g. algorithm) that it is to execute. When the audiodata subsequently arrives, the processing module 12 to 20 processes theaudio data to generate processed data (see block 120) that is thenprovided to the data path 22. Thereafter, the method 110 repeats itsmonitoring functionality as described herein. It is to be appreciatedthat any of the methodologies described herein may be provided on anymachine-readable medium. Accordingly, the invention extends to amachine-readable medium embodying a sequence of instructions, that whenexecuted by a machine, cause the machine to execute the functionalitydescribed herein.

In one embodiment of the invention, the digital processing device 30 isin the form of a VLSI chip. The DSP module 12 may be a 32-bitfixed/floating point DSP that executes four interleaved threadssimultaneously. The device 30 may, for example, include one or more ofthe following:

-   -   200 MHz internal clock;    -   threaded interleaved architecture DSP with 1200 MFLOPS;    -   the DSP may dedicate independent DMA controllers to access host        memory/SD RAM;    -   the delay module 14 may support fractional delay lengths and        1024 memory accesses;    -   the mixer module 20 may be a 4096 channel floating-point audio        mixer;    -   a 5632 channel self ramping parameter generator may be provided;    -   the sample rate converter module 16 may be a 256 channel, hybrid        sample rate converter;    -   the filter module 18 may be a 512 channel second order digital        filter;    -   the interface module 38 may be a PCI-X interface for interfacing        the device 30 to 100 MHz SD RAM interfaces;    -   four stereo I²S digital inputs may be provided;    -   four stereo I²S digital outputs may be provided;    -   four stereo S/PDIF inputs configurable as eight channel C/DIF        inputs may be provided;    -   four stereo S/PDIF outputs configurable as eight channel C/DIF        outputs may be provided;    -   PLL slave capability to I²S and S/PDIF or C/DIF inputs may be        provided;    -   16 independent configurable general purpose input output pins        may be provided on the chip; and    -   EPROM interfaces for overwriting reset defaults may be provided.

In one embodiment, the device 30 may be connected to a general purposemicroprocessor either through the interface module 38 or through anembedded microprocessor bus interface. The microprocessor may controlthe device 30, for example, through the routing controller 52 which,accordingly, may define a host interface. External SD RAM connected tothe audio memory transport module 32 may be provided in certainembodiments. In one embodiment, the audio bus 46 may be sample locked at48 kHz to each processing module 12 to 20, 32, 34. In one embodiment,the audio bus 46 provides 256 dedicated 32-bit input channels and,accordingly, the data path interface 70 may include 256 32-bit inputchannels and 256 32-bit output channels. As mentioned above, the outputchannels may be predefined or dedicated and the input channels may beprogrammable. As mentioned above, the device 30 may include a linkedlist 100 and, in one embodiment, the DSP module 12 includes 256 inputchannels that are mapped to the 4096 channels of the audio bus 46 usingthe linked list 100. In one embodiment, whenever the DSP module 12writes to an audio output channel of the audio bus 46 in a given sampleperiod, the audio data written is transferred to the audio bus 46 and anaudio ring valid bit may then be set for the particular channel duringthe next sample period. The parameter bus 48 may provide 256 32-bitinput/output channels for parameter passing or routing.

In one embodiment, any input channel or time-slot of the audio bus 46(regardless of whether it is data used by other modules on the audio bus46) may be available for use as a sample-locked 32-bit inter-thread datachannel visible to all processing modules 12 to 20, 32, 34 This mayprovide a primary mechanism to the device 30 for passing data betweentime domain DSP threads located in different processor modules 12 to 20,32, 34. When an unused output buffer channel or time-slot is used forinter-thread data passing, the passed data may appear as valid on theaudio bus 46 in the time-slot allocated for the particular output bufferchannel or time-slot.

Data written to an available input or output audio bus buffer forinter-thread data passing may be immediately visible to all otherthreads for the remainder of the sample period in which it was written.

Thus, method and device to process digital media streams have beendescribed. Although the present invention has been described withreference to specific exemplary embodiments, it will be evident thatvarious modifications and changes may be made to these embodimentswithout departing from the broader spirit and scope of the invention.Accordingly, the specification and drawings are to be regarded in anillustrative rather than a restrictive sense.

1. A digital processing integrated circuit to process media data, theintegrated circuit including: a data path arranged within the integratedcircuit in a ring configuration to communicate the media data atdifferent sampling rates synchronized with a sample-locked rate; aplurality of processing modules positioned within the data path toprocess the media data; a routing controller; and a digital interface tocommunicate with a device external to the integrated circuit, whereinthe data path comprises a plurality of separate portions to communicatedata between adjacent of the processing modules, the separate portionsof the data path to couple the adjacent processing modules in series tocommunicate the media data between the adjacent processing modules,wherein the routing controller is configured to clock the media data intime-slots between the adjacent processing modules around the separateportions of the data path to provide communications from a sourceprocessing module to a target processing module, wherein a number of thetime-slots available for each of the different sampling rates isinversely related to each different sampling rate, and wherein eachprocessing module is assigned a fixed output time-slot and a variableinput time-slot.
 2. The integrated circuit of claim 1, wherein the datapath includes a digital audio bus that interconnects the plurality ofprocessing modules in series, wherein data is communicated around thering configuration in a single direction on the data path betweenadjacent processing modules, wherein when the source and targetprocessing modules are non-adjacent processing modules, the media datais clocked through one or more intervening processing modules, whereinat least one of the processing modules comprises a sample rate convertermodule to convert digital audio data between two of the differentsampling rates, and wherein a differing number of the time-slots is usedto communicate the digital audio data at the different sampling rates.3. The integrated circuit of claim 1, wherein media data correspondingto different processing modules is present at the same time on the datapath.
 4. The integrated circuit of claim 3, wherein each processingmodule is assigned at least one time-slot into which data processed bythe particular processing module is exported to the digital audio busand wherein data corresponding to different processing modules ispresent at the same time on the data path.
 5. The integrated circuit ofclaim 3, wherein one of the processing modules is a Digital SignalProcessor (DSP) and the data path communicates processing control datain time-slots that are allocated to the processing modules under controlof the DSP.
 6. The integrated circuit of claim 1, wherein the separateportions of the data path comprise time division multiplexed buses tocommunicate a plurality of audio channels.
 7. The integrated circuit ofclaim 1, wherein the media data path includes a total number oftime-slots for communicating media data at the different sampling rates,and wherein the sum of a number of time-slots allocated to each of thedifferent sampling rates equals the total number of time-slots.
 8. Theintegrated circuit of claim 1, wherein each processing module isconfigured to: selectively extract media data for processing from afirst of the separate portions of the data path, the media data beingprovided in at least one time-slot of the first portion of the data pathallocated to the processing module; selectively insert processed mediadata into its allocated time-slot on a second of the separate portionsfor receipt by a next processing module; and pass media data that itreceives and that is associated with other processing modules unchangedalong the second of the separate portions for receipt by the nextprocessing module.
 9. The integrated circuit of claim 1, wherein thenumber of processing modules connected along the data path isconfigurable, each processing module included in the device beingallocated at least one time-slot provided by the data path.
 10. Theintegrated circuit of claim 1, wherein the data path includes a controldata path to communicate processing control data to at least oneprocessing module, the processing control data being used by theprocessing module to process digital data received from the data path.11. The integrated circuit of claim 10, wherein the processing controldata includes parameters for digital signal processing by the processingmodule.
 12. The integrated circuit of claim 11, wherein the parametersinclude at least one of filter parameters, time delay parameters, mixingparameters, or sample-rate conversion parameters.
 13. The integratedcircuit of claim 10, wherein the control data path is a time divisionmultiplexed bus arranged to interconnect the plurality of modules in thering configuration and wherein while the media data is communicated fromthe source processing module to the target processing module, any one ormore of the processing modules can add media data to or receive mediadata from the media data path.
 14. The integrated circuit of claim 10,wherein the processing control data includes streams of processingcontrol data each of which is associated with a stream of media datacommunicated via the data path, each stream of processing control databeing destined for an associated target processing module to which thestream of media data is communicated.
 15. The integrated circuit ofclaim 14, wherein each stream of processing control data is arranged tobe communicated via the control data path to arrive at its associatedtarget module prior to a source processing module exporting the mediadata to the media data path.
 16. The integrated circuit of claim 1,wherein the data path includes: a plurality of media channels defined bytime division multiplexed time-slots; and a channel identification pathincluding channel identification data to identify each media channel tothe plurality of processing modules.
 17. The integrated circuit of claim16, wherein the data path includes a control data path to communicateprocessing control data to at least one processing module, the controldata path including a plurality of control channels defined by timedivision multiplexed time-slots, wherein the channel identification pathidentifies both the media channels and the control channels.
 18. Theintegrated circuit of claim 1, wherein the data path includes atransport bus to communicate data between an external memory that isseparate from the integrated circuit and at least one of the pluralityof processing modules of the integrated circuit.
 19. The integratedcircuit of claim 1, wherein the plurality of processing modules aredigital audio processing modules selected from the group consisting ofan audio memory transport module, a digital delay line module, a samplerate converter module, a filter module, a mixer module, a DSP module,and a digital Input/Output module.
 20. The integrated circuit of claim1, wherein the integrated circuit is in a very large scale integration(VLSI) device.
 21. The integrated circuit of claim 1, wherein eachprocessing module includes an input to receive data in a first time-slotsent by a first adjacent processing module over a first of the separateportions, and an output to send data in a second time-slot to a secondadjacent processing module over a second of the separate portions toallow serial interconnection of the processing modules in the ringconfiguration.
 22. The integrated circuit of claim 21, wherein the inputincludes at least one input register connected by the data path to thefirst adjacent processing module, and the output includes at least oneoutput register connected by the data path to the second adjacentprocessing module and media data is clocked along the data path by theat least one input register and the at least one output register.
 23. Adigital processing integrated circuit to process media data, theintegrated circuit including: a media data path arranged within theintegrated circuit in a ring configuration to communicate the media dataat different sampling rates synchronized with a sample-locked rate; aplurality of processing modules positioned within the media data pathand coupled in series to process the media data; a processing controldata path to communicate processing control data between the adjacentprocessing modules, wherein the processing control data definesprocessing functionality at an associated processing module and whereineach processing module of the plurality of processing modules isconfigured to communicate the media data and the processing control datato an adjacent processing module; the integrated circuit including arouting controller to route the media data and the processing controldata along the data path to an associated processing module; and adigital interface to communicate media data with a device external tothe integrated circuit, wherein the media data is clocked by the routingcontroller in time-slots between adjacent processing modules aroundseparate portions of the data path to provide communications from asource processing module to a target processing module, wherein a numberof the time-slots available for each of the different sampling rates isinversely related to each different sampling rate, and wherein eachprocessing module is assigned a fixed output time-slot and a variableinput time-slot.
 24. The integrated circuit of claim 23, wherein atleast one of the processing modules comprises a sample rate convertermodule to convert digital audio data between two of the differentsampling rates, and wherein a differing number of the time-slots is usedto communicate the digital audio data at the different sampling rates.25. A method to process media data in a plurality of processing modulesin a digital media processing integrated circuit, the method including:communicating, at each processing module within the integrated circuit,the media data from the processing module to an adjacent processingmodule along a data path inter connecting the plurality of processingmodules in a ring configuration until media data from a sourceprocessing module is received at a target processing module of theplurality of processing modules, the media data being communicated atdifferent sampling rates synchronized with a sample-locked rate; andcommunicating media data between the data path and a device external tothe integrated circuit, wherein the processing modules are positionedwithin the data path and coupled in series, wherein the media data isclocked in time-slots between adjacent processing modules aroundseparate portions of the data path to provide communications from thesource processing module to the target processing module, wherein anumber of the time-slots available for each of the different samplingrates is inversely related to each different sampling rate, and whereineach processing module is assigned a fixed output time-slot and avariable input time-slot.
 26. The method of claim 25, which includescommunicating the media data sequentially between the plurality ofprocessing modules, wherein at least one of the processing modulescomprises a sample rate converter module to convert digital audio databetween two of the different sampling rates, and wherein a differingnumber of the time-slots is used to communicate the digital audio dataat the different sampling rates.
 27. The method of claim 25, wherein thedata path includes a processing module identifier that identifies thesource processing module that provides the media to the data path, andwherein when the source and target processing modules are non-adjacentprocessing modules, the media data is clocked through one or moreintervening processing modules.
 28. The method of claim 25, lastprocessing module of the plurality of processing modules is communicatedto first processing module of the plurality of processing modules. 29.The method of claim 25, wherein the method includes providing theprocessed media data into a time-slot associated with a sourceprocessing module and wherein data corresponding to different processingmodules is present at the same time on the data path.
 30. The method ofclaim 25, wherein the data path includes a digital media path and aprocessing control path, the method including: providing the media datain the form of audio data to the digital media path; and providingprocessing control data to the processing control data path, theprocessing control data controlling the processing of the audio data bythe target processing module.
 31. The method of claim 25, wherein duringthe assigned fixed output time-slot, each processing is configured tooutput to the digital audio bus, and wherein during the assignedvariable input time-slot, each processing module is configured toreceive data from the digital audio bus for processing by the particularprocessing module.
 32. The method of claim 25, wherein one of theprocessing modules is a Digital Signal Processor (DSP), the methodincluding communicating processing control data via the data path intime-slots that are allocated to the processing modules under control ofthe DSP.
 33. The method of claim 25, wherein the data path is timedivision multiplexed bus including a plurality of audio channels. 34.The method of claim 33, which includes communicating data between theplurality of processing modules at the different sampling rates.
 35. Themethod of claim 34, wherein the data path includes a total number oftime-slots for communicating media data at the different sampling rates,the method including allocating a number of time-slots to each one ofthe different sampling rates so that a sum of the number of slotsallocated equals the total number of time-slots.
 36. The method of claim25, wherein the number of processing modules connected in series by thedata path is configurable, the method including allocating at least onetime-slot provided by the data path to each processing module to allowdata corresponding to different processing modules to be present at thesame time on the data path.
 37. The method of claim 25, which includescommunicating processing control data to at least one target processingmodule via a control data path, the processing control data being usedby the target processing module to process digital data received from amedia data path.
 38. The method of claim 37, which includes processingthe media data using the processing control data that includesparameters for digital signal processing.
 39. The method of claim 38,which includes communicating parameters including at least one of filterparameters, time delay parameters, mixing parameters, or sample-rateconversion parameters to a processing module via the control data path.40. The method of claim 37, which includes communicating the processingcontrol data in a time division multiplexed fashion.
 41. The method ofclaim 37, wherein the processing control data includes streams ofprocessing control data each of which is associated with a stream ofmedia data communicated via the media data path, each stream ofprocessing control data being destined for an associated targetprocessing module to which the stream of media data is communicated. 42.The method of claim 41, which includes communicating each stream ofprocessing control data via the control data path to arrive at itstarget processing module prior to exporting the media data from itssource processing module to the media data path.
 43. The method of claim25, wherein the data path includes: a plurality of media channelsdefined by time division multiplexed time-slots; and a channelidentification path including channel identification data to identifyeach media channel to the plurality of processing modules.
 44. Themethod of claim 43, which includes communicating processing control datato at least one target processing module via a control data path, thecontrol data path including a plurality of control channels defined bytime division multiplexed time-slots, wherein the channel identificationpath identifies both the media channels and the control channels. 45.The method of claim 25, which includes communicating data between anexternal memory that is separate from the integrated circuit and atleast one of the plurality of processor modules via a transport bus ofthe integrated circuit.
 46. the method of claim 25, which includescommunicating media data between digital audio processing modulesselected from the group consisting of an audio memory transport module,a digital delay line module, a sample rate converter module, a filtermodule, a mixer module, a DSP module, and a digital Input/Output module.47. A computer-readable that stores a sequence of instructions forexecution by one or more processors to perform the following operationsto process media data in a plurality of processing modules byconfiguring the processing modules to: communicate, at each processingmodule within the integrated circuit, the media data from the processingmodule to an adjacent processing module along a data pathinterconnecting the plurality of processing modules in a ringconfiguration until media data from a source processing module isreceived at a target processing module of the plurality of processingmodules, the media data being communicated at different sampling ratessynchronized with a sample-locked rate; and communicate media databetween the data path and a device external to the integrated circuitvia a digital interface, wherein the processing modules are positionedwithin the data path and coupled in series, wherein the media data isclocked between adjacent processing modules around separate portions ofthe data path to provide communications from the source processingmodule to the target processing module, wherein a number of thetime-slots available for each of the different sampling rates isinversely related to each different sampling rate, and wherein eachprocessing module is assigned a fixed output time-slot and a variableinput time-slot.
 48. The computer-readable medium of claim 47, whereinthe media data is communicated sequentially between the plurality ofprocessing modules, wherein at least one of the processing modulescomprises a sample rate converter module to convert digital audio databetween two of the different sampling rates, and wherein a differingnumber of the time slots is used to communicate the digital audio dataat the different sampling rates.
 49. The computer-readable medium ofclaim 47, wherein the data path includes a processing module identifierthat identifies the source processing module that provides the media tothe data path.
 50. The computer-readable medium of claim 47, whereinmedia data received at a last processing module of the plurality ofprocessing modules is communicated to first processing module of theplurality of processing modules.
 51. The computer-readable medium ofclaim 47, wherein the processed media data is provided in a time-slotassociated with a source processing module and wherein datacorresponding to different processing modules is present at the sametime on the data path.
 52. The computer-readable medium of claim 47,wherein the data path includes a digital media path and a processingcontrol path, the instructions being to: provide the media data in theform of audio data to the digital media path; and provide processingcontrol data to the processing control data path, the processing controldata controlling the processing of the audio data by the targetprocessing module.
 53. The computer-readable medium of claim 47, whereineach particular processing module is assigned at least one programmableor fixed time-slot of a digital audio bus defined by the data path, andwherein digital audio data processed by the particular processing moduleis exported to the programmable or fixed time-slot.
 54. Thecomputer-readable medium of claim 53, wherein one of the processingmodules is a Digital Signal Processor (DSP), and wherein processingcontrol data is communicated via the data path in the time-slots thatare allocated to the processing modules under control of the DSP. 55.The computer-readable medium of claim 54, wherein the data path includesa total number of time-slots for communicating media data at thedifferent sampling rates, and wherein a number of time-slots areallocated to each of the different sampling rates so that a sum of thenumber of time-slots allocated to each of the different sampling ratesequals the total number of time-slots.
 56. The computer-readable mediumof claim 47, wherein the data path is a time division multiplexed busincluding a plurality of audio channels.
 57. The computer-readablemedium of claim 56, wherein data is communicated between the pluralityof processing modules at the different sampling rates.
 58. Thecomputer-readable medium of claim 47, wherein the number of processingmodules connected in series by the data path is configurable and whereinat least one time-slot is provided by the data path to each processingmodule to allow data corresponding to different processing modules to bepresent at the same time on the data path.
 59. The computer-readablemachine readable medium of claim 47, wherein processing control data iscommunicated to at least one target processing module via a control datapath, the processing control data being used by the target processingmodule to process digital data received from a media data path.
 60. Thecomputer-readable medium of claim 59, wherein the media data isprocessed using the processing control data that includes parameters fordigital signal processing.
 61. The computer-readable medium of claim 60,wherein parameters including at least one of filter parameters, timedelay parameters, mixing parameters, and sample rate conversionparameters are communicated to a processing module via the control datapath.
 62. The computer-readable medium of claim 59, wherein theprocessing control data includes streams of processing control data eachof which is associated with a stream of media data communicated via themedia data path, each stream of processing control data being destinedfor an associated target processing module to which the stream of mediadata is communicated.
 63. The computer-readable medium of claim 62,which includes communicating each thread of processing control data viathe control data path to arrive at its target processing module prior toexporting the media data from its source processing module to the mediadata path.
 64. The computer-readable medium of claim 47, wherein thedata path includes: a plurality of media channels defined by timedivision multiplexed time-slots; and a channel identification pathincluding channel identification data to identify each media channel tothe plurality of processing modules.
 65. The computer-readable medium ofclaim 64, wherein processing control data is communicated to at leastone target processing module via a control data path, the control datapath including a plurality of control channels defined by time divisionmultiplexed time-slots, wherein the channel identification pathidentifies both the media channels and the control channels.
 66. Thecomputer-readable medium of claim 47, wherein data is communicatedbetween an external memory and at least one of the plurality ofprocessor modules via a transport bus.
 67. The computer-readable mediumof claim 47, media data is communicated between digital audio processingmodules selected from the group consisting of an audio memory transportmodule, a digital delay line module, a sample rate converter module, afilter module, a mixer module, a DSP module, and a digital Input/Outputmodule.